Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be configured to provide user-defined features. PLDs are often implemented with multiple memory arrays to store data, such as configuration data, user data, or other data.
During the manufacture of such PLDs, each memory array is typically tested to confirm proper operation. For example, test data values may be programmed into a memory array of a PLD. Data values stored by the memory array may then be read out from the memory array and compared to the original test data values. In this regard, data values stored by the memory array may be provided to a data shift register (DSR) which shifts the stored data values to appropriate testing logic to determine whether the stored data values corresponds to the original test data values programmed into the memory array.
Because the DSR is generally shared between the various memory arrays, testing is typically performed only on one memory array at a time. For example, in a PLD having separate non-volatile and volatile memory arrays, the non-volatile memory array (e.g., a flash memory array) is generally tested separately from the volatile memory array (e.g., a static random access memory (SRAM) array). As a result, the testing time associated with multiple memories is a significant portion of the overall PLD testing time, especially in cases where read margin tests are performed using different read reference voltages. Although certain PLDs may allow simultaneous execution of multiple memory instructions during testing, such implementations may still cause contention due to the use of a shared DSR.
Accordingly, there is a need for an improved approach to PLD testing. In particular, there is a need for an approach that reduces testing time without unduly increasing the size and complexity of PLD test circuitry.